FIG. 1 illustrates a conventional circuit 10 for driving a pair of signals, such as complementary CMOS input signals “in_p” and “in_n”. The circuit 10 includes a first set 12 of drivers or inverters inv1, inv2, inv3, inv4; and a second set 14 of drivers or inverters inv5, inv6, inv7, inv8. The output of the circuit of FIG. 1 includes two signals “out_p” and “out_n” that have been amplified and driven by the first or second set 12, 14 of inverters/drivers.
As recognized by the present inventor, in such a design of FIG. 1, any skew between the two input signals 16, 18 (such as a time delay or offset between the two input signals) will be transmitted to the outputs “out_p” and “out_n” because the two strings 12, 14 of drivers are independent. Also, to the extent that there are any process mismatches in the inverter/driver components (inv1, inv2, . . . inv8) or other signals components, or to the extent that there may be coupling of noise into one of the string of drivers which is not equally coupled into the other string of drivers, additional skew may appear at the outputs.
As recognized by the present inventor, what is needed is a circuit for driving complementary input signals through the use of drivers or inverters to produce complementary driven output signals while reducing the amount of skew between the driven output signals.
It is against this background that various embodiments of the present invention were developed.